Present complementary metal oxide semiconductor (CMOS) synchronous dynamic random access memory (SDRAM) circuits are frequently used for main memory in a variety of applications including desk top and portable computer systems. Advances in system technology require ever increasing clock rates and memory bus widths to achieve high data rates. Both of these methods, impose equally demanding limitations on memory testers that must guarantee functionality of the memory circuits under all conditions. Previous memory design-for-test circuits have logically combined multiple data bits extracted from a memory array in parallel to produce an equivalent compressed bit. The memory tester evaluated this representative compressed bit of the multiple data bits, thereby reducing the apparent size of the memory circuit to be tested. But this test method is still inefficient due to the greater operating speed of state-of-the-art memory circuit than of current memory testers. Current memory testers, therefore, significantly constrain memory circuit production. An upgrade of memory testers, however, would require a significant expenditure of capital.
This limitation of memory testers is particularly apparent for synchronous dynamic random access memory (SDRAM) circuits operating in burst mode. An SDRAM circuit receives initial row and column address signals in a burst read cycle. An internal address counter increments this initial address to produce parallel sequences of data bits corresponding to each bit position of a data word in synchronization with a system clock signal. Although, the SDRAM circuit may potentially operate faster than the memory tester, both input and output data rates of the sequences of data bits are limited by the speed of the memory tester. Thus, the memory tester severely limits SDRAM production even with highly parallel DFT circuits of the prior art.